C-DAC Bengaluru Project Engineer VLSI ME Recruitment 2026

C-DAC Bengaluru Project Engineer VLSI ME is available through the official recruiting body. C-DAC Bengaluru has published an official notice for Project Engineer (VLSI ME). This guide summarises the verified application details and VLSI chip design, RTL synthesis, physical design verification, and FPGA prototyping. This article summarises the verified notice and keeps the official application route below.

The notification is Advt. No. C-DAC/BLR/02/2026. The location context is Bengaluru, Karnataka, India. Candidates should use the full notice for category, reservation, and post-specific conditions.

C-DAC Bengaluru Project Engineer VLSI ME: Quick Facts

Recruiting body	C-DAC Bengaluru
Post or examination	Project Engineer (VLSI ME)
Notification	Advt. No. C-DAC/BLR/02/2026
Vacancies	25 Posts
Location	Bengaluru, Karnataka, India
Important dates	Online applications close on 20 June 2026 at 18:25 IST

Vacancies, Pay, Fee and Important Dates

The official vacancy position is 25 Posts. Initial CTC ranges from Rs. 4.49 LPA to Rs. 7.11 LPA based on experience

The application schedule is: Online applications close on 20 June 2026 at 18:25 IST. The fee position is: Refer to the official careers portal for fee payment instructions. Applicants should complete payment and final submission before the stated deadline.

Eligibility and Age Conditions

Eligibility must be complete by the date stated in the notice. A similar course name does not automatically qualify unless the recruiting body accepts it.

• BE/B.Tech or equivalent degree with 60% or equivalent CGPA; or Post Graduate degree in Science/Computer Applications with 60% or equivalent CGPA; or ME/M.Tech; or Ph.D. in relevant discipline.
• Strong understanding of hardware description languages (Verilog, SystemVerilog, or VHDL).
• Familiarity with digital circuit design, RTL simulation, physical design verification, or static timing analysis.
• Strong conceptual knowledge of digital systems, CMOS cell characteristics, and timing specifications is required.

Selection Process

The recruiting body controls shortlisting and can apply the conditions in the official notice. Candidates should track notices, email, and the application portal after submission.

• Develop and verify RTL modules for digital microprocessors or custom accelerator blocks.
• Perform logic synthesis, placement, routing, and physical verification checks.
• Conduct static timing analysis (STA) and optimize chips for power, performance, and area (PPA).
• Prototype and debug designs on high-performance FPGA evaluation boards.
• Write comprehensive test benches using SystemVerilog or UVM to verify design correctness under various corner cases.

Documents to Keep Ready

Names, dates, marks, and category details should match the supporting records. Correct discrepancies before document verification whenever the rules allow it.

• Education certificates and complete marksheets.
• Date-of-birth and government identity proof.
• Experience or service certificates in the required format.
• Category, disability, NOC, vigilance, or deputation records where applicable.
• Submitted application, fee receipt, photograph, and signature records.

Checks Before Final Submission

Use the preview or print view before final submission. Correcting a form later may be restricted, may require a fee, or may not be available for every field.

• Confirm that the selected post, category, centre, and qualification are correct.
• Check spelling of the candidate name and parents' names against official records.
• Verify marks, passing dates, certificate numbers, and experience periods.
• Open each uploaded file once to confirm it is clear and in the required format.
• Make sure payment status and final-submission status both show completion.

How to Apply Through the Official Route

• Read the official notification and confirm qualification, age, category, and post conditions.
• Register only on the official recruiting portal using an active email and mobile number.
• Enter details exactly as shown in educational and identity documents.
• Upload the required files, pay the fee when applicable, and complete final submission.
• Download the submitted form or confirmation page and keep the registration details secure.

Avoid agents, unofficial forms, copied notices, and payment requests sent through social media. Government recruitment does not require a private person to secure selection.

Preparation Guidance

Use the syllabus or role criteria from the official notice as the preparation boundary. Do not spend time on an exam stage or subject that the notice does not include.

• Revise digital logic design, Verilog coding standards, setup/hold constraints, and clock domain crossing solutions.
• Study ASIC design flow stages from RTL to GDSII.
• Understand clock domain crossing (CDC) issues, reset synchronization, and low-power design techniques like clock gating.

Recheck the official website for corrigenda, date changes, admit cards, and result notices. Selection depends on the notified process, document checks, and applicable rules.

Frequently Asked Questions

How many posts are available?

There are 25 contract vacancies advertised for the VLSI ME role.

What is the age limit?

The upper age limit is 30 years for freshers and up to 45 years for experienced candidates.

What is the official source?

The source is the official C-DAC Bengaluru notice hosted through careers.cdac.in. The apply button uses the official route.